1. Field of the Invention
The invention relates to a chip carrier for semiconductor chips, and more specifically, to a power, ground and decoupling lead structure whereby a minimum number of chip carrier leads are utilized for power and ground connection and whereby a decoupling capacitor is provided in close proximity to the chip.
2. Description of the Prior Art
Chip carriers for integrated circuit chips are well known in the art and are widely used. Such chip carriers have lead arrays thereon which extend from the outer edge of the chip carrier to a central portion of the carrier where they are then connected to bonding pads on semiconductor chips bonded at and to the center of the chip carrier. In these prior art circuits, in order to provide power and/or ground voltages to the appropriate pads on the chip, it has been necessary to use a plurality of these leads on the chip carrier for such purpose. This is due to the fact that the leads on the chip are thin and easily overloaded. For this reason, many leads in parallel have been used to minimize lead resistance. This is wasteful and, also, since the number of leads on the chip is limited, the number of external connections from the chip carrier that can be made is therefore reduced. In addition, the prior art systems have required the use of a discrete decoupling capacitor separate and relatively distant from the chip and chip carrier.